library ieee ;
use ieee.std_logic_1164.all;
use work.all;


-- Definicion
entity cmp_2bits is
    port( data:  inout std_logic; 
          rwa:   in std_logic;
          rwb:   in std_logic;
          ea:    in std_logic;
          eb:    in std_logic;
          clock: in std_logic );
end cmp_2bits;


-- Arquitectura
architecture behv of cmp_2bits is

    component cmp_reg1bit
    port( data:  inout std_logic;
          rw:    in std_logic;
          e:     in std_logic;
          clock: in std_logic );
    end component;

begin
    reg1bitA: cmp_reg1bit port map (data, rwa, ea, clock);
    reg1bitB: cmp_reg1bit port map (data, rwb, eb, clock);
end behv;
